Nvidia Pours Billions Into Advanced Chip Packaging to Ease AI Bottleneck

A global race to build AI infrastructure has turned advanced chip packaging from an afterthought into the primary choke point for the world's most powerful processors. Nvidia is providing billions of dollars in financing to expand CoWoS (chip-on-wafer-on-substrate) capacity at Siliconware Precision Industries (SPIL), a unit of Taiwan's ASE Technology, according to a single unnamed industry executive cited by Reuters [4]. The scale of Nvidia's support had not previously been reported [5].

The CoWoS crunch

Taiwan Semiconductor Manufacturing Company (TSMC) dominates CoWoS, the packaging technology that mounts processor and memory chips on a shared base so they can exchange data at high speed. Nvidia, AMD, Broadcom and cloud providers building custom silicon all rely on it [4]. But TSMC's capacity limits have left chip designers scrambling for alternatives. "Demand is extraordinary. Capacity is the constraint," Nvidia CEO Jensen Huang said in October [5][6].

Advanced packaging revenue is forecast to overtake traditional packaging for the first time in 2026, with capital spending on the technology expected to near $28 billion, according to research firm Yole Group [2][4]. Former Intel CEO Pat Gelsinger, now a partner at Playground Global, estimates packaging could eventually account for as much as half a chip's value, as today's GPUs and CPUs integrate 10 or more chips, sometimes as many as 20 [1][2][4].

Nvidia's supply-chain bets

Nvidia's financing for SPIL will fund new factory space and equipment [4]. The company did not respond to requests for comment; ASE said it does not comment on market rumours involving its customers [2][4].

The SPIL deal is part of a broader push. At its GTC Berlin event, Nvidia announced a suite of capacity-reservation agreements: a multibillion-dollar advance to Japanese substrate maker IBIDEN targeting 3x capacity at its Ono plant by early 2028; a $1.1 billion advance to chip-testing firm KYEC for new U.S. facilities targeting high-volume production in April 2027; a partnership with Unimicron in Taiwan to add substrate capacity by mid-2028; a plan with Amkor in South Korea targeting a greater than 300% increase in interposer wafer capacity (more than quadruple) by end-2028; and an expansion with SPIL for optical engines used in co-packaged optics, targeting a 15x increase by mid-2027 and a further doubling by end-2028 [6]. Nvidia's own press release describes the SPIL partnership as targeting optical engines for co-packaged optics, not CoWoS capacity expansion [6].

ASE CFO Joseph Tung said on an October earnings call that the company raised its 2026 capital spending budget from $10.5 billion to $11.5 billion, expects full-process advanced-packaging revenue to more than triple from $300 million this year to over $1 billion in 2027, and warned that next year's demand could far exceed what ASE can supply [5]. Tung also said ASE could turn to customer financing to help fund expansion [5], speaking generally rather than about Nvidia specifically [2].

Rivals and alternatives

AMD has announced more than $10 billion of investment across Taiwan's semiconductor ecosystem, including packaging partnerships with ASE, SPIL and Powertech Technology (PTI) [1][2][4]. "I think CoWoS and advanced packaging are super important for our high-performance computing going forward," AMD CEO Lisa Su told Reuters in October. "TSMC has been an incredible partner... and yes, we do need more capacity overall" [1][4].

PTI, chaired by D.K. Tsai, is betting on panel-level packaging, which uses rectangular panels instead of round wafers to fit more chips per run and cut material waste as AI processors grow larger [1][2][4]. "Everyone is looking for a solution outside TSMC. They don't want to rely entirely on TSMC," Tsai said in August [4]. PTI is working with AMD and Broadcom to prove the technology for large-scale AI applications and plans a $400 million advanced-packaging joint venture with Broadcom in Singapore, with production that could begin in 2028 [1][2][4]. PTI Senior Vice President Jim Lin said capacity is the most important issue right now, with customers waiting for the company to ramp up [4].

TSMC is developing its own panel-based technology, called CoPoS (chip-on-panel-on-substrate). In April (per a statement earlier this year) it said it had built a pilot line and expected production within a couple of years, though CoWoS remains its main AI packaging technology [2][4]. Microsoft Azure hardware chief Rani Borkar said panel-level packaging would cut material waste for larger AI chips, though Microsoft has not decided whether or when to adopt it [2][4].

Equipment makers pivot

Equipment makers are also pivoting. Tokyo Electron Taiwan president Seiji Nakama said advanced packaging is growing much faster than the chipmaking equipment market, though it remains smaller [4]. Applied Materials vice president Sree Kesapragada said the market, including panel-level technology, could grow significantly within three to five years: "It's near-term," he said. "It's not like, 10 years, 15 years off" [4].

What is clear: the bottleneck is real, the capital is flowing, and multiple firms are building alternatives to TSMC's CoWoS lines. How quickly those alternatives reach volume, and whether panel-level packaging proves viable for the largest AI chips, remains to be seen.